Senior Verification Engineer – 12301

Veritaz is a leading IT staffing solutions provider in Sweden, committed to advancing individual careers and aiding employers in securing the perfect talent fit. With a proven track record of successful partnerships with top companies, we have rapidly grown our presence in the USA, Europe, and Sweden as a dependable and trusted resource within the IT industry.


Assignment Description:
We are looking for a Senior Verification Engineer to join our dynamic team.
What you will work on:
Participate in ASIC verification activities across multiple projects
Collaborate in teams handling IP design and subsystem integration/verification
Apply UVM methodology for verification of complex ASIC or large FPGA designs
Perform IP block verification, including modules with multiple clock domains
Contribute to developing and maintaining robust test benches

What you bring:
Minimum 5 years of experience in ASIC verification
Strong knowledge of UVM and SystemVerilog
Proven experience with complex ASIC and/or large FPGA systems
Background in verifying IP blocks with multi-clock domain considerations
Excellent English communication skills, both written and verbal
Familiarity with AXI5 and ACE5 protocols (meritorious)
Experience using Cadence tools, particularly Xcelium (meritorious)
Understanding of test bench architecture and structure (meritorious)
Leadership skills and ability to guide peers (meritorious)
Knowledge of RTL design principles (meritorious)
Scripting skills for automation (meritorious)
Exposure to the telecom domain (meritorious)

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